1. Field of the Invention
The present invention relates to an optical disk driving device for driving a CD-R, on which data can be recorded, a CD-RW, on which data can be rewritten, and, in particular, to a recording timing control circuit for such an optical disk driving device.
2. Description of the Related Art
As a type of compact disk, a CD-R (CD recordable: recording can be performed only once), a CD-RW (CD rewritable: recording can be performed a plurality of times), and a CD-E (also called a CD erasable) are known.
On these CD-R and CD-RW disks (hereinafter, referred to as CD-R/RW), pregrooves are formed as guide tracks for information recording.
The pregroove wobbles right and left in the shape of a sine curve with a center frequency of 22.05 kHz.
Further, the pregroove is obtained as a result of FM modulation being performed with a modulation factor of +/-1 kHz from the center frequency of 22.05 kHz corresponding to a time code which indicates time information for each sector.
Accordingly, by performing FM demodulation on the wobbling frequency, a time code indicating the time information can be obtained.
The time information recorded as a wobbling signal of the pregroove is called ATIP (Absolute Time In Pregroove).
The ATIP includes not only the time information but also an ATIP synchronization signal and a CRC code.
A format of an ATIP frame will now be described.
As shown in FIG. 1, The ATIP frame includes the synchronization signal (Sync), minutes, seconds, frames and the CRC code (CRC remainder). The data of minutes, seconds and frames is also called MSF (Minutes, Seconds, Frame) data.
The ATIP synchronization signal has a pattern such as that shown in FIG. 2.
FIG. 2 shows one example for the ATIP synchronization signal.
The pattern of the ATIP synchronization signal (SYNC) is `11101000`, as shown in FIG. 2, as channel bits, when the immediately prior cell=0, and the synchronization signal has the signal waveform (pattern) as shown in FIG. 2. When the immediately prior cell=1, the pattern of the ATIP synchronization signal is the pattern of `00010111` as channel bits.
In a driving device (hereinafter, referred to as a CD-R/RW drive) which can record information on the CD-R/RW, the ATIP is detected, the time information of the current sector is detected and the sector from which information is to be recorded is determined.
Information later recorded on the CD-R/RW has a format the same as the format of a CD (Compact Disk).
On the CD, a subcode frame synchronization signal is recorded in information later recorded.
A position relationship between the ATIP synchronization signal included in the pregroove of the CD-R/RW and the subcode frame synchronization signal included in information later recorded will now be described.
In part 2 of the Orange Book which is known as a book of standards for the CD-R, it is prescribed that the position displacement between the ATIP synchronization signal and the subcode frame synchronization signal included in information later recorded is to be within a predetermined value.
FIG. 3 shows a position relationship between the ATIP synchronization signal included in the pregroove of the CD-R/RW and the subcode frame synchronization signal included in information later recorded.
As shown in FIG. 3, the position displacement between the ATIP synchronization signal (ATIP SYNC) and the subcode frame synchronization signal (SUBCODE SYNC) is to be within the predetermined value.
When the position displacement between the two synchronization signals becomes larger, in a case where information is recorded on a not-yet-recorded area subsequent to an already-recorded area on a disk, overlapping of two pieces of recorded information may occur, the overlapped portion may be large, and thereby, reproduction may be impossible. Conversely, when a space between adjacent pieces of recorded information is large, synchronization detection cannot be performed and, similarly, reproduction is impossible.
FIG. 4 shows a general functional block diagram of a portion of an example of a recording timing-control circuit in a CD-R/RW drive in the related art. This portion includes an EFM encoder 41 and an ATIP decoder 42. In FIG. 4, EFM is a pattern to be recorded, SUBSYNC is a subcode frame synchronization signal insertion timing signal, EXTSYNC is a synchronization request signal, EXTACK is a synchronization completion signal, ATIPSYNC is an ATIP synchronization detection signal, BICLKIN is a biphase clock signal and BIDATAIN is biphase data.
The biphase data BIDATAIN and the biphase clock signal BICLKIN are input to the ATIP decoder 42. The biphase data BIDATAIN is obtained as a result of FM demodulation being performed on the wobbling signal of the pregroove by an external FM demodulating circuit. The biphase clock signal BICLKIN is extracted from the biphase data BIDATAIN by an external clock extracting circuit.
The ATIP decoder 42 detects the time information of the ATIP and detects the ATIP synchronization signal from the biphase data BIDATAIN and biphase clock signal BICLKIN.
When the ATIP synchronization signal is detected, the ATIP synchronization detection signal ATIPSYNC is output.
The EFM encoder 41 modulates data to be recorded so as to cause the data to have a predetermined CD format, and outputs the pattern to be recorded (EFM).
Further, the EFM encoder 41 inserts the subcode frame synchronization signal into the pattern to be recorded (EFM).
In this case, at the timing at which the subcode frame synchronization signal is inserted, the EFM encoder 41 outputs the subcode frame synchronization insertion timing signal SUBSYNC.
Timing initialization of the EFM encoder 41, which is performed prior to recording information will now be described.
FIG. 5 shows a timing chart for illustrating operations of the timing initialization of the EFM encoder 41. The reference symbols given to the respective waveforms correspond to the reference symbols shown in FIG. 4, respectively.
In the CD-R/RW drive, before information recording is started, the synchronization request signal EXTSYNC is input to the EFM encoder 41, in order to perform initialization so that the position displacement between the ATIP synchronization signal (ATIP SYNC) and the subcode frame synchronization signal (SUBCODE SYNC) is to be within a predetermined range. In FIG. 5, the sign `-` is given to the synchronization request signal EXTSYNC. This sign `-` means that the period during which the synchronization request signal is generated is the period during which the waveform is at a low level.
When the synchronization request signal EXTSYNC is input, the EFM encoder 41 outputs the subcode frame synchronization signal insertion timing signal SUBSYNC so that the subcode frame synchronization signal should be inserted immediately after the detection of the ATIP synchronization signal, for example, within 1 EFM frame from the output of the ATIP synchronization detection signal ATIPSYNC.
Thus, the timing initialization of the EFM encoder 41 is performed.
When the timing initialization is performed, the EFM encoder 41 outputs the synchronization completion signal EXTACK.
The recording timing control circuit shown in FIG. 4 operates as described above, and, the timing from the detection of the ATIP synchronization signal to the insertion of the subcode frame synchronization signal is fixed.
The prior art relating to an optical disk driving device according to the present invention will now be described.
First, as the prior art, a circuit which detects accompanying information, such as that described above, from the wobbling of the pregroove on CD-R is known (for example, Japanese Laid-Open Patent Application No.6-290462).
This circuit for detecting accompanying information is well-known.
Then, a phase synchronization circuit, a so-called digital PLL, used in a digital system, such as digital audio equipment and so forth, is conventionally known (for example, Japanese Laid-Open Patent Application No.2-3137).
This phase synchronization circuit (digital PLL) includes a phase comparator, a digital integrator and a variable frequency divider.
The phase comparator performs phase comparison between an input signal and a reproduced clock signal from the PLL. The thus-obtained phase error signal is integrated by the digital integrator. In accordance with the thus-obtained integrated value, the frequency dividing ratio of the variable frequency divider is determined.
Hereinafter, such a digital PLL is referred to as first prior art.
Further, as related art, as a digital filter, an FIR (Finite Impulse Response) filter is known (for example, Japanese Laid-Open Patent Application No.2-50363).
This FIR filter includes an m-bit parallel delay element, multiplier and accumulator used in a filtering operation.
The delay element latches data at a rising edge of a data latch signal.
The operation result of n bits is output from the accumulator which adds the outputs of the multiplier.
Hereinafter, such a FIR filter is referred to as a second prior art.
As related art described above, a timing from detection of the ATIP synchronization signal to insertion of the subcode frame synchronization signal is fixed.
Accordingly, when the timing of detecting the ATIP synchronization signal is delayed from a timing corresponding to the position of the actual ATIP synchronization signal recorded on the disk, due to delay of biphase data output in the FM demodulating circuit and delay of detection of the ATIP synchronization signal in the ATIP decoder, the timing of inserting the subcode frame synchronization signal is delayed and the insertion position of the subcode frame synchronization signal is displaced. As a result, the position relationship shown in FIG. 3 cannot be maintained.
Therefore, as described above, in a case where information is recorded on a not-yet-recorded area subsequent to an already-recorded area, an overlapped portion may be large, and thereby, reproduction may be impossible. Conversely, when a space between a pair of adjacent pieces of recorded information is large, synchronization detection cannot be performed and, similarly, reproduction is impossible.